Resolution enhancement techniques and OPC(Optical Proximity Correction) have been developed with empirical data points from general test patterns and some actual patterns extracted from full-chip design. Lithography simulation tools have been used for intensive process simulation to optimize RET solutions using sample patterns to cover whole full-chip patterns. However, as design complexity increases and mask manufacturing rules restrict process proximity correction coverage, post-RET/OPC data can generate fatal patterning failures at locations where the process window is marginal. Therefore, it is necessary to identify those patterns from full-chip layout to choose proper RET/OPC solutions. Previously, it was proven that model based full-chip verification tool is useful to capture potential fatal patterning failures before mask tape-out sign-off for sub-wavelength lithography processes.  In this paper, we extended the full-chip verification methodology to quantitative RET/OPC development using database error analysis. First, using GDS data containing design intent only and a single 90nm lithography process calibrated model, we performed full-chip verification for linearly scaled designs through 130nm, 90nm and 65nm node to take OPC directions. Second, a standard OPC recipe was applied for each design node followed by verification. And then, potential pattern failures at 65nm node were analyzed through lithography process window. Finally, RET/OPC solution was discussed for 65nm design.