19 January 2005 Self-alignment method by buried mask implantation for double gate MOS and nanodevices fabrication
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Proceedings Volume 5592, Nanofabrication: Technologies, Devices, and Applications; (2005) https://doi.org/10.1117/12.572660
Event: Optics East, 2004, Philadelphia, Pennsylvania, United States
Two methods to build submicronic self-aligned devices based on SOI MOS technology have been studied. The foreseen application of these techniques is the fabrication of self-aligned double gate SOI MOS transistors. Both of these methods make use of the implantation of a buried mask underneath the active silicon layer and aligned with the top gate. The mask is revealed by a selective etching between doped and undoped polysilicon. In one case Tetra-methyl Ammonium hydroxide solution (TMAH) is used to create a negative mask, etching the undoped zones. In the second case, a positive mask is revealed in a solution made of Hydrofluoric acid, Nitric acid and Acetic acid (HNA), etching the doped zones. Once the mask is revealed, the process differs from a normal CMOS process by the addition of two Chemical Mechanical Polishing (CMP) and bonding steps. The realized demonstrator proves the feasibility of both the positive and negative buried mask.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Remy Charavel, Remy Charavel, Jean-Pierre Raskin, Jean-Pierre Raskin, } "Self-alignment method by buried mask implantation for double gate MOS and nanodevices fabrication", Proc. SPIE 5592, Nanofabrication: Technologies, Devices, and Applications, (19 January 2005); doi: 10.1117/12.572660; https://doi.org/10.1117/12.572660


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