25 October 2004 Two-dimensional optoelectronic interconnect-processor and its operational bit error rate
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Abstract
Two-dimensional (2-D) multi-channel 8x8 optical interconnect and processor system were designed and developed using complementary metal-oxide-semiconductor (CMOS) driven 850-nm vertical-cavity surface-emitting laser (VCSEL) arrays and the photodetector (PD) arrays with corresponding wavelengths. We performed operation and bit-error-rate (BER) analysis on this free-space integrated 8x8 VCSEL optical interconnects driven by silicon-on-sapphire (SOS) circuits. Pseudo-random bit stream (PRBS) data sequence was used in operation of the interconnects. Eye diagrams were measured from individual channels and analyzed using a digital oscilloscope at data rates from 155 Mb/s to 1.5 Gb/s. Using a statistical model of Gaussian distribution for the random noise in the transmission, we developed a method to compute the BER instantaneously with the digital eye-diagrams. Direct measurements on this interconnects were also taken on a standard BER tester for verification. We found that the results of two methods were in the same order and within 50% accuracy. The integrated interconnects were investigated in an optoelectronic processing architecture of digital halftoning image processor. Error diffusion networks implemented by the inherently parallel nature of photonics promise to provide high quality digital halftoned images.
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J. Jiang Liu, Brian Gollsneider, Wayne H. Chang, Gary W. Carhart, Mikhail A. Vorontsov, George J. Simonis, Barry L. Shoop, "Two-dimensional optoelectronic interconnect-processor and its operational bit error rate", Proc. SPIE 5595, Active and Passive Optical Components for WDM Communications IV, (25 October 2004); doi: 10.1117/12.573130; https://doi.org/10.1117/12.573130
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