Resolution Enhancement Techniques (RET) in lithography have enabled optical lithography to reliably produce IC features 2 or even 3 times smaller than the optical wavelength used for imaging. At this point, even the dimensions required for the 32nm node appear to be in reach using 193nm photons, provided hyper-NA lenses and extreme RET solutions are also adopted. In this paper, the development of RET over the past century is briefly reviewed, to better understand how we made it so far using what we have. Current trends for some of the most recent developments in implementing the 65nm IC node are presented. These include novel illumination source optimization algorithms and polarization considerations. This is followed by a general consideration of whether lessons learned from these applications can be applied to other situations currently described as Design for Manufacturing (DFM) technologies. Consideration will also be given to the extension to DFM for other photonic structures, such as photonic crystal switching devices.

Extensive usage of Litho RET, Etch trimming and OPC techniques has become common practice in the integrated patterning flow for 90nm and beyond. In this paper, we will discuss our approach to use OPC for both etch and litho through-pitch bias correction for a 90nm contact layer. In stead of using conventional lumped model, [J.P. Stirniman, M.L. Rieger, SPIE Proc. Optical/Laser Microlithography X, Vol. 3051, p294, 1997], we introduced an alternative modeling approach to reduce our model correction into: Corrected Mask Layout = T_mask^-1 (T_optical^-1 (T_etch^-1 (Design Layout) ) ). Post OPC checking using Synopsys SiVl platform shows that CD 3σ = 7.82nm of through-pitch OPC residual error. This study also shows that integrated patterning flow combined with LRC tools is useful to provide feedback to the designer and highlight some patterning process limitation that is design dependent.

To extend the application of current optical lithographic tools to next generation production technology, it is necessary to reduce the k1 factor in Rayleigh's resolution equation. Double dipole lithography (DDL) is one of the candidates for a low-k1 imaging technique and it is a viable solution for 65- and 45-nm technology nodes. Because DDL takes has the advantage of extreme off-axis illumination of the dipole, the printing capability of small features as well as their through-pitch common process window can be enhanced. However, as a dipole illuminator gains the benefits of high contrast only for structures perpendicular to the dipole orientation, the original mask layout must be converted into horizontal and vertical components and printed in a double exposure. Throughput will be sacrificed due to the multiple exposures. Nevertheless, DDL mask manufacture is relatively simple compared to the production of the more complicated phase shift mask (PSM) and chromeless phase lithography (CPL). As regards an overlay issued from the separate image composition, several papers have shown the minor effect on pattern fidelity using the current ArF scanner. To split the design layout according to the pattern orientation, the double exposure scheme needs an automatic layout conversion algorithm. To integrate the H V conversion with model- and/or rule-based optical proximity corrections (OPCs), several approaches for pattern decomposition associated with OPC treatment have been suggested. In this paper we will go over the development of model- and rule-based OPC treatment and will focus on current technology for accurate model-based OPC development with empirical model calibration. Using the technique the lithographic performances such as pattern fidelity, process window as well as overlay error sensitivity will be demonstrated. We focus on a 65-nm technology node with k1 near 0.31. Based on the success of tool development and verification, the DDL with full-chip OPC-treated decomposition will become a mature low-k1 imaging solution.

For 90nm node generation, 65nm, and beyond, dark field mask types such as contact-hole, via, and trench patterns that all are very challenging to print with satisfactory process windows for day-to-day lithography manufacturing. Resolution enhancement technology (RET) masks together with ArF high numerical aperture (NA) scanners have been recognized as the inevitable choice of method for 65nm node manufacturing. Among RET mask types, the alternating phase shifting mask (AltPSM) is one of the well-known strong enhancement techniques. However AltPSM can have a very strong optical proximity effect that comes with the use of small on-axis illumination sigma setting. For very dense contact features, it may be possible for AltPSM to overcome the phase conflict by limiting the mask design rules. But it is not feasible to resolve the inherent phase conflict for the semi-dense, semi-isolated and isolated contact areas. Hence the adoption of this strong enhancement technique for dark filed mask types in today’s IC manufacturing has been very limited. In this paper, we present a novel yet a very powerful design method to achieve contact and via masks printing for 90nm, 65nm, and beyond. We name our new mask design as: Novel Improved Contact-hole pattern Exposure PSM (NICE PSM) with off-axis illumination, such as QUASAR. This RET masks design can enhance the process window of isolated, semi-isolated contact hole and via hole patterns. The main concepts of NICE PSM with QUASAR off-axis illumination are analogous to the Super-FLEX pupil filter technology.

The use of Alternating phase-shifting mask has been demonstrated to be a most powerful approach to expand resolution limitation and expand the process window of lithography. But the phase conflict problem limits the application of alt-PSM. For dark field alt-PSM, node connection PSM is a feasible method to solve the problem. We investigate the application of this method at 100nm node by simulation with ArF light source. The results prove that alt-PSM with conventional partial coherence illumination can be applied in the manufacturing of random interconnect layer. This method can expand the process window effectively. The program that can achieve the pattern decomposition automatically is also developed. We’re sure that combined with optical proximity effect correction, this multi-exposure technology can fulfill the need of 0.1-μm generation logic IC lithography.

In the 30 years since lithography modeling was first introduced, optical lithography simulation has progressed from a curiosity, to a research and development tool, and finally to a manufacturing tool. While much has been published on new developments in lithography simulators and their use in advanced lithography development, less is published on how simulators have been used and are soon to be used in semiconductor manufacturing flows. This review paper will describe the most popular and useful examples today for lithography simulators in a manufacturing environment.

Inductively coupled plasma (ICP) technology is a new advanced version of dry-etching technology compared with the widely used method of Reactive Ion Etching (RIE). Extensive experiments have been done successfully and the fabrication results of microoptical elements have proved that the new ICP technology is very effective in dry etching field. Plasma processing of the ICP technology is complicated due to the mixed reactions among discharge physics, chemistry and surface chemistry. Existing models concentrate only on part of the whole problem, for example, on plasma physics, or on chemistry reactions. Despite the efforts to understand and model the etching process, simulation of the surface phenomena with accurate and general model coefficients is still lacking. Need for a simulation is even greater when high-density plasma methods such as inductively coupled plasma (ICP) technology are used due to strong polymer deposition effects. In the paper we analyze the physical reactions and chemical reactions that may occur in the chamber in detail, and a surface dynamic model is used to explain the complex reactions occurring in the reaction chamber. At last, we present an experiment that demonstrates the applicability of the surface dynamic model theory very well. The surface dynamic model of the ICP technology presented in this paper provides us a theory basis so that we can take effective measures to control the etching process of ICP technology and to improve the etching quality of microoptical elements greatly.

To accelerate the time-to-market of advanced photomasks, Photronics launched its 90nm program in spring 2003. The program included three learning cycles and a technology transfer phase. Both 90nm test masks and product masks from leading integrated device manufacturers (IDMs) and foundries were exercised through the cycles. Stringent success criteria were set based on a survey of leading customers’ requirements and the International Technology Roadmap for Semiconductors (ITRS). Hundreds of binary masks, embedded attenuated phase shift masks (EAPSMs), and alternating aperture phase shift masks (AAPSMs) were produced throughout the program. All targets were exceeded. This paper describes program success criteria, complexity of customer requirements, 90nm test vehicle design, and efforts on improving critical dimension (CD) uniformity and registration. Results in positive and negative chemically amplified resist (CAR) and tunable etching for AAPSM are shown. Details on AAPSM undercut optimization, intensity and CD imbalance are reported.

For 90nm node and beyond technology generations, one of the most critical challenges is how to meet the local CD uniformity (proximity) and global CD uniformity (GCDU) requirements within the exposure field. Both of them must be well controlled in the mask making process: (1) proximity effect and, (2) exposure pattern loading effect, or the so-called e-beam "fogging effect". In this paper, we report a method to improve our global CDU by means of a long range fogging compensation together with the Leica SB350 MW. This exposure tool is operated at 50keV and 1nm design grid. The proximity correction is done by the software - package "PROXECCO" from PDF Solutions. We have developed a unique correction method to reduce the fogging effect in dependency of the pattern density of the mask. This allows us to meet our customers’ CDU specifications for the 90nm node and beyond.

Haze is a kind of surface contamination on photomask and lithography optics that made by photochemical reaction. There are many problems in photomask manufacturing, inspection and lithography process because of slowly growing feature of haze. In the photolithography process, the wafer damage has been occurred due to the time dependent growth of haze. In this study, we identified the origin and formation mechanism of haze using accelerated contamination experiments, also developed control methods for haze. From these results we expect that the photocontamination control technology should be developed and been a important part of NGL technology.

The chromeless phase lithography (CPL) is a potential technology for low k1 optical image. For the CPL technology, we can control the local transmission rate to get optimized through pitch imaging performance. The CPL use zebra pattern to manipulate the pattern local transmission as a tri-tone structure in mask manufacturing. It needs the 2^nd level writing to create the zebra pattern. The zebra pattern must be small enough not to be printed out and the 2^nd writing overlay accuracy must keep within 40nm. The request is a challenge to E-beam 2^nd writing function. The focus of this paper is in how to improve the overlay accuracy and get a precise pattern to form accurate pattern transmission. To fulfill this work several items have been done. To check the possibility of contamination in E-Beam chamber by the conductive layer coating we monitor the particle count in the E-Beam chamber before and after the coated blank load-unload. The conductivity of our conductive layer has been checked to eliminate the charging effect by optimizing film thickness. The dimension of alignment mark has also been optimized through experimentation. And finally we checked the PR remain to ensure sufficient process window in our etching process. To verify the performance of our process we check the 3D SEM picture. Also we use AIMs to prove the resolution improvement capability in CPL compared to the traditional methods-Binary mask and Half Tone mask. The achieved overlay accuracy and process can provide promising approach for NGL reticle manufacturing of CPL technology.

Shrinkage of device dimensions requires tighter lithography process control. Current levels of Process Control leave less than 0.5 nm budget for CD metrology. An accurate and stable metrology solution requires measurement of CD and profile that are critically dependent on thin film material characterization at various earlier process stages. Opti-Probe integrates five different technologies into a single platform to accurately characterize optical properties of 193 nm materials. Real-time CD (RT/CD) technology utilizes four independent spectra collected from the samples using a rotating-compensator spectroscopic ellipsometer (RCSE) and analyzes the spectra with an innovative numerical solution-finding approach to construct detailed CD and profile of printed features in a 2- and 3 Dimensional geometries. The study presents a comparison of: i) Methodologies using an advanced combination of metrology techniques to characterize 193 nm materials (e.g. ARC). ii) Measured CD and profile variations using RCSE of Opti-Probe and RT/CD technology. iii) Correlation between measured CD variation and measured material characteristics. In order to achieve less than 0.3 nm accuracy and stability requirement for sub 65 nm process development and CD uniformity control, less than 0.003 variation and accuracy in optical dispersion (n&k) of critical material has to be ensured.

The rapid shrink of device dimensions requires not only excellent 1D CD precision, but also characterization of corner rounding and line end shape. To meet this on-going trend the industry is in a quest for higher resolution metrology tools, which in-turn drives the use of SEM metrology as more crucial. The industry challenge is to reduce corner rounding and area loss. The metrology challenge, is to be able to measure accurately and precisely these characters, in order to be able to control your process. In our study we will introduce the development of a new algorithm for general shape analysis. The purpose of this algorithm is to allow effective control of the correspondence of the feature’s shape to the design geometry. The disadvantage of the standard CD SEM metric such as contact area was discussed widely in the literature but new metrics were not discussed yet. We consider the following issues and challenges related to the development of a generic algorithm for general shape 2D analysis. First stage of this algorithm is a generic segmentation of the two dimensional features. It should be robust to noise, as well as brightness and contrast changes. Output of this phase will be the contour representing the bottom of the feature. The second stage is the obtaining of new CD metrics for these contours, especially for contours corresponding to contacts with OPC structures. We consider the corner rounding as an example of such new metric. The same techniques can be elaborated for a large range of 2D structures with different levels of complexity. The obtaining of new metrics can be useful as handles for advanced process control (i.e. what to measure on the 2D feature with complex shape such as contact with OPC structures). We consider in this paper the application of the developed metrics for reticle contact with OPC structure monitoring problem that simulates a high level of complexity.

A method was developed to measure hydrocarbons to 1 part-per-trillion (ppt) concentration levels with a gas chromatograph and flame ionization detector (GC/FID). This method was used to measure purifier siloxane removal efficiencies from air under dry and humid conditions. Several media types were examined: activated carbon (AC), bead-shaped activated carbon (BAC) and a proprietary inorganic material (PIM). Under dry conditions, all three materials removed the siloxane challenge to below 1ppt. The AC material had a removal efficiency of 286 ppt under humid conditions. The BAC and PIM removed the siloxane challenge to below 1 ppt under humid conditions. After media saturation was reached under humid conditions, the materials were regenerated and siloxane removal efficiencies were re-examined. Only the PIM material was regenerable to below 1ppt efficiency levels.

Downscaling of semiconductor fabrication technology nodes brought forth a need to reassess the accuracy of 3D metrology. Accuracy is defined relative to a reference tool measurement. The authors have studied the accuracy of 3D SEM measurement results for various feature geometries and materials, matching the results to Monte Carlo simulations. Analysis of the SEM images based on an analytical model was performed. Careful analysis of the matching curves for 3D algorithm results and reference data (geometric parameters of the feature) reviled an appropriate behavior of algorithm in the vicinity of the nominal process window, and for sufficiently small feature rounding (production node). We performed matching of 3D CD SEM measurement to reference geometry data using Monte Carlo simulation. We analyzed the accuracy of measurement for a wide range of the feature geometry parameters (height, sidewall angle, top and bottom rounding). The simple physical model for corner rounding estimation is considered. We perform the model waveform analysis of the feature rounding influence on the height measurements. Serving as a process-monitoring tool, the algorithm performance was found in agreement with the required tolerance typical of the nominal process window ± 10%. Serving on extreme R&D, where rounding further away from the nominal window ± 10% is counted significant, there lie observable deviations in accuracy of height and sidewall angle measurement. These are explained through extreme corner rounding effects.

An effective and simple method to determine the energy range of FOCAL is described in this paper. Relationship between the chop line width and defocus is analyzed. Simulated curves of the chop line width versus defocus are obtained by PROLITH. By choosing the curves which satisfy certain conditions, the energy range of FOCAL is determined off line. Independent of the lithographic tool, the method is time-saving and effective. The influences of some process factors, e.g. resist thickness, PEB temperature, PEB time and development time, on the energy range of FOCAL are analyzed.

Since the early 1980's, the resolution of optical projection lithography has improved dramatically primarily due to three factors: increases in projection lens numerical aperture, reduction of the imaging source wavelength, and continued reduction of the k1 factor. These three factors have been enabled by the concurrent improvements in lens making technology, DUV light sources, photoresist technology, and resolution enhancement techniques. The DUV light source, excimer KrF and ArF lasers, has entered main stream production and now images more than 50% of the critical layers in today's leading edge devices. Looking forward to both immersion lithography and beyond to EUV lithography, new light source technologies must be created to enable the continued progression of shrinking feature sizes embodied by Moore's law.

For 193-nm lithography, water proves to be a suitable immersion fluid. ArF immersion offers the potential to extend conventional optical lithography to the 45-nm node and potentially to the 32-nm node. Additionally, with existing lenses, the immersion option offers the potential to increase the focus window with 50% and more, depending on actual NA and feature type. In this paper we discuss the results on imaging and overlay obtained with immersion. Using a 0.75 NA ArF projection lens, we have built a proto-type immersion scanner using TWINSCAN technology. First experimental data on imaging demonstrated a large gain of depth of focus (DoF), while maintaining image contrast at high scan speed. For first pilot production with immersion, a 0.85 NA ArF lens will be used. The resolution capabilities of this system will support 65 nm node semiconductor devices with a DOF significantly larger than 0.5 um. Early imaging data of such a system confirms a significant increase in focus window.

As feature size decreases, especially with the use of resolution enhancement technique such as off axis illumination and phase shifting mask, fast and accurate in-situ measurement of coma has become very important in improving the performance of modern lithographic tools. The measurement of coma can be achieved by the transmission image sensor, which is an aerial image measurement device. The coma can be determined by measuring the positions of the aerial image at multiple illumination settings. In the present paper, we improve the measurement accuracy of the above technique with an alternating phase shifting mask. Using the scalar diffraction theory, we analyze the effect of coma on the aerial image. To analyze the effect of the alternating phase shifting mask, we compare the pupil filling of the mark used in the above technique with that of the phase-shifted mark used in the new technique. We calculate the coma-induced image displacements of the marks at multiple partial coherence and NA settings, using the PROLITH simulation program. The simulation results show that the accuracy of coma measurement can increase approximately 20 percent using the alternating phase shifting mask.

The use of immersion technology will extend the lifetime of 193nm and 157nm lithography by enabling numerical apertures (NA) much greater than 1.0. The ultimate limits of NA are explored by analysis of polarization effects at the reticle and imaging effects at the wafer. The effect of Hertzian or micro-polarization due to the size of the reticle structures is examined through rigorous simulation. For the regime of interest, 20nm to 50nm imaging, it is found that dense features on a Cr binary reticle will polarize the light into the TE component upwards of 15%. Below this regime, the light becomes polarized in the TM direction. The use of polarization in the illuminator for imaging will result in substantial gains in exposure latitude and MEF when the NA~1.3 with 45nm lines at 193nm. The end-of-line pullback for 2-dimensional patterns is reduced by the use of TE polarization in the illuminator. The overall polarization effects increase with decreasing k₁. The interaction between the reticle induced polarization and the illumination polarization is shown to be significant when an analysis is done using rigorous mask simulation instead of the more common Kirchhoff approximation.

Exposure dose control technique in step-and-scan exposure lithography systems is discussed. The dose control principle for step-and-scan system is analyzed in depth. A dose control algorithm is proposed. Measurements of dose accuracy and repeatability are made on an experiment setup. Dose accuracy of 1.37% and dose repeatability of 0.31% are obtained using this dose control technique. Experiment results indicate that this dose control technique meets the requirement of sub-half-micron lithography.

The Aerial Image Measurement System (AIMS) for 193nm lithography emulation is established as a standard for the rapid prediction of wafer printability of critical features, such as dense patterns or contacts, defects or repairs on masks. The benefit of AIMS is to save expensive image qualification consisting of test wafer exposures followed by wafer SEM measurements. By adjustment of numerical aperture, illumination type and partial coherence to match the stepper or scanner, AIMS predicts the printability of any 193nm reticle like binary, OPC and PSM. The newly available 193nm 2^nd generation AIMS fab systems are able to emulate numerical apertures (NA) up to 0.92 and provide a capability down to 65nm node regardless of the use of an immersion liquid or dry conditions. Rigorous simulation studies have been performed to study the matching of AIMS and scanner results at NA = 0.92 and to study the extension of the AIMS technique for immersion lithography emulation of hyper NA up to at least 1.4. Strong polarization effects depending on mask patterns and material as well as imaging effects will occur below the 65nm node. It will be shown that using the polarization capabilities of such a future immersion AIMS tool will provide a very suitable immersion lithography emulator. Together with low k1 values and polarization effects, 193nm mask design and manufacturing will face increased challenges for design and OPC placement at the 65nm node and below. Aerial image measurements of test masks using AIMS will then be crucial to speed up mask development. We propose to measure reticles on critical points as defined by simulation or areas of concern for manufacture with the AIMS system to analyze defect printability and mask manufacturability.

FOCAL is an on-line measurement technique of the imaging parameters of a lithographic tool with high accuracy. These parameters include field curvature, astigmatism, best focus and image tilt. They can be acquired by the least-square algorithm from the alignment positions of the special marks on the exposed wafer. But the algorithm has some intrinsic limits which may lead to a failure of the curve fitting. This will influence the measurement accuracy of the imaging parameters obtained by FOCAL. Therefore, a more reliable algorithm for the FOCAL technique is needed. In this paper, the feed-forward back-propagation artificial neural network algorithm is introduced in the FOCAL technique, and the FOCAL technique based on BP ANN is proposed. The effects of the parameters, such as the number of neurons on the hidden-layer, the number of training epochs, on the measurement accuracy are analyzed in detail. It is proved that the FOCAL technique based on BP-ANN is more reliable and it is a better choice for measurement of the imaging parameters.

Two-photon absorption (TPA) is confined at the focus under tight-focusing conditions, which provides a novel concept for micro-fabrication using two-photon photo-polymerization in resin. The development of three-dimensional micro-fabrication by femtosecond laser was introduced at first, then the merits of femtosecond two-photon photo-polymerization was expatiated. Femtosecond laser direct scanning three-dimensional (3D) micro-fabrication system was set up and corresponding controlling software was developed. We demonstrated a fabrication of three-dimensional microstructures using photo-polymerization of resin by two-photon absorption. The precision of micro-machining and the spatial resolution reached 1um because of TPA. The dependence of fabricated line width to the micro-fabrication speed was investigated. Benzene ring, CHINA and layer-by-layer of log structures were fabricated in this 3D- micro-fabrication system as examples.

In this paper, patterning SiO₂ thin film on the Si (100) surface was successfully demonstrated using a synchrotron radiation (SR) stimulated etching technique with SF₆ + O₂ as the reaction gas and a Co contact mask. The contact Co contact mask on the SiO₂ surface was fabricated by sputtering Co film on a photolithography resist pattern and lift-off technique. The thickness of the Co mask measured using a step profile meter was about 145 nm. The SR irradiation with flowing SF₆ and O₂ can effectively etch the silicon dioxide and the etching process stop at the silicon surface. The etching rate was found to increase with decreasing the substrate temperature. The Co mask was found to show sufficient resistivity for the SR etching. The etched pattern was evaluated by scanning electron microscopy (SEM) and step profile meter.

The process of resist is of great importance to the resolution of e-beam direct-writing exposure. ZEP520 is an excellent positive e-beam resist, which has high resolution, high sensitivity, high contrast as well as good dry etch resistance. In this paper, the e-beam exposure process of ZEP520 on Si and GaAs substrates and its application in nanoelectrode-pair and single-electron transistor have been studied. On Si substrate, the contrast, sensitivity and resolution of ZEP520 have been investigated in detail, and the influence of exposure dose and resist thickness on the size of ZEP520 patterns has been discussed. The contrast of 425nm-thick ZEP520 on Si is 2.70. The sensitivity of ZEP520 is <5 μC/cm². The size of ZEP520 lines and circular holes decreases with exposure dose decreasing and thickness increasing. 70 nm wide lines and 110-nm-diameter dots can be exposed on Si substrate using 110 nm thick ZEP520. The flaws of ZEP520 on GaAs can be eliminated by fore-baking the GaAs substrate; and 130 nm wide lines can be exposed on GaAs using ZEP520. In regard to application, a nanoelectrode-pair with a 60 nm space has been fabricated using ZEP520. And a kind of in-plane singe-electron transistor (SET) has also been fabricated on silicon-on-insulator (SOI) substrate, which has a 110 nm wide Si Coulomb island and shows Clear Coulomb staircases in I_ds from the I_ds-V_ds characteristics and differential conductance (dI_ds/dV_ds) oscillations from the dI_ds/dV_ds-V_ds characteristics at 2 K.

In view of some problems of the thermal cross-linking CTP plate previously prepared in our laboratory, an acid proliferation generator was synthesized and used in the preparation of CTP plate. Therefore, the sensitivity and imaging quality of CTP plate was improved obviously. This kind of plate has an imaging layer, comprising an admixture of a resole resin, a novolac resin, a latent Bronsted acid, an acid proliferation generator, an infrared absorber and colorant. The plate is intended for digital exposure with an infrared laser with 830nm in a computer to plate (CTP) machine. The dot density of the printing plate ranges from 1 to 99 percent, and the resolution can reach 6μm. On the aspect of making printing plate these characteristics achieve acceptable criterion of printing.

Some research results in advanced optical lithography, Electron beam lithography, X-ray lithography are introduced in this paper. For advanced optical lithography, optical proximity correction and phase-shift masking (PSM) are studied, and 150nm pattern is achieved by i-line Stepper using transparent PSM. For e-beam lithography, the resist process, proximity effect correction and mix & match technologies are investigated, and 27nm CMOS device is successfully fabricated. The 0.15μm GaAs PHEMT devices are successfully fabricated by employing X-ray lithography.

We developed a UV assisted soft nanoimprint lithography (UV-SNIL) that can be applied for the reproduction of nanometer features over large areas. Based on a simple argument deduced from the Navier-Stokes equation, we suggest several solutions to enhance the imprinting process ability. One of the solutions is to use tri-layer soft stamps, which consists of a rigid carrier, a low Young's module buffer and a top layer supporting nanostructure patterns to be replicated. Typically, the buffer and the top layer are made of polydimethylsiloxane (PDMS) of 5 mm thickness and polymethylmetacrylate (PMMA) of 10-50 μm thickness respectively. Patterning of the stamp top layer can be done in three different ways, i.e., spin coating, nano-compression and direct writing, all resulting in 100 nm features over a large wafer area. Another solution is to use a bilayer resist system for which imprinting is performed on the top layer while the final pattern is obtained by transferring the top layer image into the bottom layer by reactive ion etching. Comparing to other imprint techniques, UV-SNIL works at room temperature and low pressure, which is applicable for a wafer-scale replication at high throughput. For the research purpose, we also demonstrate nanostructure fabrication by lift-off techniques.

Most applications of Mo/Si multilayer optics in Extreme ultraviolet lithography (EUVL) require a high normal incidence reflectivity. Using dc magnetron sputtering we achieved R = 68.8 % @ λ = 13.45 nm. High-reflective Mo/Si/C and high-temperature stable Mo/C/Si/C multilayer mirrors with reflectivity of 69.6 % and 61.0 % at 13.5 nm were developed. Microstructure and optical properties of the multilayers have been investigated by small and large angle Cu-Kα scattering and characterized by EUV reflectivity. Beside the periodic multilayer design, Mo/Si multilayer mirrors with increased as well as reduced bandwidth in their spectral and angular reflectance have been designed and deposited. A reflectivity of more than 20 % was achieved in the wavelength range from 13 nm to 15 nm. In addition, narrowband multilayer mirrors with a significantly reduced band-width (FWHM = 0.077 nm) basing on high order reflection have been designed and fabricated. Both the increase and the reduction of the reflection bandwidth are unavoidably connected with a decrease of peak reflectivity. Therefore, the application of such specially designed mirrors involves areas where a maximum peak reflectivity is not required, e.g. in EUV spectroscopy and for the metrology of EUV sources. According to the optics requirements of an EUVL tool, the accurate deposition of high reflective and laterally graded multilayers on ultraprecise polished substrates can be regarded as one of the major challenges of EUVL development today. To meet these requirements, a new dc magnetron sputtering system has been developed.

In this paper, Beam Propagation Method (BPM) with Fast Fourier Transforms(FFT) is employed to efficiently calculate the diffract image in the wafer plane for both conventional and second generation synchrotron-based proximity x-ray lithography(PXL). In the simulation, a dark-field isolated space pattern silicon nitride/Ta x-ray mask is used for conventional PXL and a diamond /Ta x-ray mask is used for second generation PXL, the diffract image’s dependency on absorber thickness, mask-wafer gap, effective total blur, linewidth and absorber sidewall slope has been numerically evaluated. For conventional PXL, in order to obtain a isolated trench resolution of 50nm, the mask-wafer gap should be controlled below 5 micron, the optimization condition is mask-wafer gap 5 micron, Ta absorber thickness 300nm, effective total blur 10nm, absorber sidewall slope 3°, the corresponding aerial image contrast is 0.457; For second generation, in order to obtain a isolated trench resolution of 50nm, the mask-wafer gap can be as large as 10 micron. In order to obtain a isolated trench resolution of 35nm, mask-wafer gap should be controlled below 5 micron.

A maskless lithography imaging simulation using digital micromirror device (DMD) was investigated. The DMD acts as a reflective spatial light modulator. The micro-mirrors on DMD can be instructed by the computer to tilt them ±12° off their normal position which produces a mask pattern, and then the mask pattern can be carried onto the surface of wafer by the imaging system. Because the imaging of the maskless lithography is a complex process, it is necessary to simulate and analyze its practical process. In this paper, we present a partial coherent imaging model of maskless lithography considering the practical projection characterization of DMD. With the model, it is convenient to simulate the lithography of arbitrarily shaped microstructure using DMD. Through calculation, the spatial image in maskless lithography process based on gray scale photolithography with DMD real-time masks was obtained.

Use of simulation-based printing verification prior to mask tapeout has become standard practice for mask layers printed with low-k1 lithography processes. At 90nm and above, this methodology has proven beneficial and sufficient for guaranteeing a usable mask. However, it is anticipated that at 65nm and below, a simulation at a single point within the process window may fail to capture all important marginal areas of a mask prior to tapeout. Modern lithography simulation tools are proven capable of accurately predicting printing behavior through process window. Unfortunately, due to long run times, use of such tools is restricted to small simulation areas. Recent developments in vectorial thin-film OPC models have enabled full process window prediction on large product die. Although such models are extremely fast compared to conventional lithography simulation tools, the prospect of simulating a full chip at multiple dose and focus points is quite daunting. In an effort to reduce the expected longer run times when simulating full chips at multiple focus and dose conditions, we have developed two flows which reduce the total run time enormously. These so-called pre-targeting flows are explained, and the limitations and future prospects of the flows are described.

As semiconductor manufacturing moves to the 90nm node and below, shrinking feature sizes and increasing IC complexity have combined to significantly stretch out the time needed to optimize and qualify process anchored OPC models and recipes. Process distortion and non-linearity become non-trivial issues and conspire to reduce the quality of the resulting corrections. Additionally, optimizing the OPC model and recipe on a limited set of test chip designs may not provide sufficient coverage across the range of designs to be produced in the process. Finally, the increased complexity of the transformation of the target pattern into a corrected mask pattern also increases the probability of system lithography errors. Fatal errors (pinch or bridge) or poor CD distribution may still occur. As a result, more than one reticle tape-out cycle is non uncommon to prove models and recipes that approach the center of process for a range of designs. In this paper, we describe a full-chip simulation based verification flow using a commercialized product that serves both OPC model and recipe development as well as post OPC verification after production release of the OPC.

For describing the micro-topography of a measured surface reasonably, this paper puts forward a parameter named minimal area of average height of the surface micro-topography based on the least square method, which is different from the qualitative uniformity surface parameters such as correlation theory, power spectral analysis, profile matrix spectrum and surface matrix spectrum. That means to look for the minimal size square which could represent the average height value of the sample area. If the deviation between the mean height values in this area and in the sample area is ±5% which is ±2σ of Gaussian distribution, and at the same time the ratio between the minimal area and the sample area is less than 0.8, then the measurement data from the sample area is considered as the characteristic of the measured surface micro-topography. Some standard samples finished by lapping grinding, surface grinding, planning, and end milling and plain milling are measured by using phase-shift Michelson and micro-grating-projection method in this paper. The two measurement principles are given in this paper. The R_a value of the standard samples measured and the measurement results of the minimal area of average height are given. The results shown that the parameter of minimal area of average height exist good consistency with the parameter of Ra.

T-shaped gate formation is a important process step in the fabrication of high frequency monolithic microwave integrated circuits (MMIC), many different lithography process have been used for this purpose, such as bi-layer or tri-layer using e-beam lithography, hybrid UV-e-beam lithography. Proximity x-ray lithography (PXL) has shown many advantages in the MMIC manufacturing, such as high resolution, large process windows, low cost and high throughout, and so on. In this article, a new ZEP520/P(MMA-MAA)/ZEP520 tri-layer process using synchrotron-based PXL is proposed for the T-shaped gate formation, without any additional intermediate layer, the resists intermixing problem has been solved successfully, a dark-field isolated trench x-ray mask was used for this purpose. A three stage development process using xylene for the head, MIBK:IPA=1:3 for the middle and xylene for the foot was also used. Initial work has shown this process to be robust.

Based on reactive ion etching (RIE) technology, a 2-D symmetric tetragonal and columnar subwavelength surface relief structure for infrared antireflection can be made on silicon wafer. By analyzing the impact on etch rate, anisotropy and uniformity caused by some technological parameters in reactive ion etching (RIE), parameters such as etchant gas, concentration and flow rate of the gas, pressure of reaction room and radio-frequency power density can be selected. Meanwhile, surface structure appearance, parameters and infrared transmission performance of etching sample have been measured, and the measure results have been analyzed according to technological demands.

Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning, and via fill material is required to protect etch stop layer and to provide excellent substrate reflectivity control. It also has to be completely removed after trench-etch. Organic bottom anti-reflective coating (BARC) material became a good candidate for 130nm via fill, but its shell defects in via following trench etch cause significant yield loss, especially in 90nm process and beyond with low-k dielectrics. A new SiO2 based via fill material matches plasma etch rate to SiOCH, SiOF, and SiO2 inter-layer dielectrics and prevents shell defects. It is applied by spin coating with standard bake and also highly absorbing to suppress substrate reflectivity. In this paper we integrate this SiO2 based material into 90nm Dual Damascene process. Topics such as performance in spin coating, trench lithography, plasma etching, and selective removal by wet clean will be discussed.

Polarization effects have only recently been considered an issue that is growing more for optical lithography. It has been demonstrated that wire-grid structures placed within features have the ability to polarize incident light on a mask. This paper also recognizes the advantages that can be gleamed from the polarization properties, but differs in that it attempts to use a chromium wire-grid polarization mask itself to polarize the incident light. In this paper, we explore a vector model of microlithography imaging with polarization distribution function. Polarization from chromium wire-grid polarization mask can be used as a new lever to improve lithographic performance. This paper also addresses the fundamental issues underlying the design of such a chromium wire-grid polarization mask. The influence of a chromium wire-grid polarization mask on microlithography system has been systematically investigated by comparison on the imaging contrast and the process window. We compare the effects of polarization light imaging with a conventional mask and a chromium wire-grid polarization mask at wavelength of 0.248 μm, a numerical aperture of 0.65 and a partial-coherence of 0.2. It can be concluded that a high-resolution imaging performance can be obtained by using chromium wire-grid polarization mask.

The Micro-processing & Nano-technology Laboratory at the Institute of Microelectronics, Chinese Academy of Sciences (CAS), is equipped with a GCA 3600F PG&3696, a JBX 6AII & JBX 5000LS EB, and an ETEC MEBES 4700S EB. For a long time we have been engaged in the research and manufacture on Optical Resolution Enhancement Technology (RET) and E-Beam Direct Writing Technology. In this paper the following technologies will be described: PSM, OPC EBDW,EPC,Match & Mixed Lithography technology. Through the application of RET in optical lithography system, we completed the 0.2 um pattern with the g line and I line light source, which is the necessary preparation for 100nm node with 193nm light source. By means of match & mixed lithography and nanofabrication technology, 20nm-50nm gate CMOS transistor and 100nm gate HEMT are successfully developed.

This article presents a microfabrication technology of 3D microstructures via the soft-imprint technique using poly(dimethylsiloxane) (PDMS) mold attached with a screen mask, TEM grid. A prepolymer and monomer mixture, after short UV exposure, rises only up to the open spot of TEM grid, sequentially into the groove of the PDMS mold, then, 3D microstructures are formed in one-step process. The unreacted remaining monomer enables the viscous prepolymer mixture to fill the cavity of TEM grid and the PDMS mold, and the conformal contact of the PDMS mold with TEM grid also prevents the permeation of sticky prepolymer into the interface of PDMS mold and TEM grid. The proposed technique is an inexpensive, simple, and reliable method to fabricate 3D microstructures without expensive and complex lithographic tools. Thus, using this 3D microfabrication method, various 3D microstructures of the combination of TEM grid pattern and PDMS mold groove are easily generated with good pattern fidelity.

The hybrid nanocontact printing(HnCP) method is a technology for manufacturing an ultra violet(UV) imprinted silicon substrate from a master and then printing by letting it get in contact with a substrate coated with a metal thin film. It comprises a step in which a master with a nano-pattern is prepared; a step in which the resist is applied to the surface of the silicon substrate; an imprinting step in which the master is let to get in contact with the resist surface, pressurized and then taken off; a step in which the imprinted silicone substrate is manufactured into a nanocontact stamp by curing the resist on the imprinted silicon substrate; a step of inking a self-assembled monolayer on the surface of the imprinted silicone substrate stamp; a step of transferring a printing pattern by letting the imprinted silicone substrate stamp get in contact with the substrate coated with a metal thin film; and a step of forming a desired pattern on the substrate by etching the metal thin film on the substrate to which the printing pattern has been transferred. In case the HnCP method, on which this study is conducted, is used, it enables the stamp manufacturing process to be shortened and optimized, because the nanoocontact printing process is conducted by using an imprinted silicon substrate stamp, and it has the advantage of making the stamp have a large area so that it is possible to produce it in a large quantity through a mass production process. Also, as a hard stamp is used, any error resulting from an ultra micro torsion and mismatching can be prevented in the multi-layering process, and since any deformation or defect is not brought about, the pattern's resolution can be enhanced so that it is possible to embody a pattern of 100nm.