27 January 2005 Increasing post OPC layout verification coverage using a full-chip simulation based verification method
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As semiconductor manufacturing moves to the 90nm node and below, shrinking feature sizes and increasing IC complexity have combined to significantly stretch out the time needed to optimize and qualify process anchored OPC models and recipes. Process distortion and non-linearity become non-trivial issues and conspire to reduce the quality of the resulting corrections. Additionally, optimizing the OPC model and recipe on a limited set of test chip designs may not provide sufficient coverage across the range of designs to be produced in the process. Finally, the increased complexity of the transformation of the target pattern into a corrected mask pattern also increases the probability of system lithography errors. Fatal errors (pinch or bridge) or poor CD distribution may still occur. As a result, more than one reticle tape-out cycle is non uncommon to prove models and recipes that approach the center of process for a range of designs. In this paper, we describe a full-chip simulation based verification flow using a commercialized product that serves both OPC model and recipe development as well as post OPC verification after production release of the OPC.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chi-Yuan Hung, Chi-Yuan Hung, Yong Dong Wang, Yong Dong Wang, Ze Xi Deng, Ze Xi Deng, Gen Sheng Gao, Gen Sheng Gao, Ming Hui Fan, Ming Hui Fan, } "Increasing post OPC layout verification coverage using a full-chip simulation based verification method", Proc. SPIE 5645, Advanced Microlithography Technologies, (27 January 2005); doi: 10.1117/12.572711; https://doi.org/10.1117/12.572711


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