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27 January 2005 Lithography yield enhancement through optical rule checking
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Use of simulation-based printing verification prior to mask tapeout has become standard practice for mask layers printed with low-k1 lithography processes. At 90nm and above, this methodology has proven beneficial and sufficient for guaranteeing a usable mask. However, it is anticipated that at 65nm and below, a simulation at a single point within the process window may fail to capture all important marginal areas of a mask prior to tapeout. Modern lithography simulation tools are proven capable of accurately predicting printing behavior through process window. Unfortunately, due to long run times, use of such tools is restricted to small simulation areas. Recent developments in vectorial thin-film OPC models have enabled full process window prediction on large product die. Although such models are extremely fast compared to conventional lithography simulation tools, the prospect of simulating a full chip at multiple dose and focus points is quite daunting. In an effort to reduce the expected longer run times when simulating full chips at multiple focus and dose conditions, we have developed two flows which reduce the total run time enormously. These so-called pre-targeting flows are explained, and the limitations and future prospects of the flows are described.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James C. Word V, J. Andres Torres, Thomas Roessler, Neal Lafferty, and Shumay Shang "Lithography yield enhancement through optical rule checking", Proc. SPIE 5645, Advanced Microlithography Technologies, (27 January 2005);


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