Resolution Enhancement Techniques (RET) in lithography have enabled optical lithography to reliably produce IC features 2 or even 3 times smaller than the optical wavelength used for imaging. At this point, even the dimensions required for the 32nm node appear to be in reach using 193nm photons, provided hyper-NA lenses and extreme RET solutions are also adopted. In this paper, the development of RET over the past century is briefly reviewed, to better understand how we made it so far using what we have. Current trends for some of the most recent developments in implementing the 65nm IC node are presented. These include novel illumination source optimization algorithms and polarization considerations. This is followed by a general consideration of whether lessons learned from these applications can be applied to other situations currently described as Design for Manufacturing (DFM) technologies. Consideration will also be given to the extension to DFM for other photonic structures, such as photonic crystal switching devices.