28 February 2005 Implementation of reconfigurable time delay digital tanlock loop
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In this paper, a first order TDTL system is designed, simulated and implemented on a reconfigurable FPGA system. Initially the loop was designed and simulated using Matlab/Simulink. Subsequently some novel modifications were introduced to the TDTL in order to allow an optimized reconfigurable implementation, which eases the design process and allows for dynamic parameter and design modifications. The reconfigurable TDTL was tested in real time conditions under the same operating conditions of the simulated loop. Comparison between the simulated and real time results indicate a high degree of correlation, making the loop attractive for various practical applications.
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Mahmoud A. Al-Qutayri, Mahmoud A. Al-Qutayri, Saleh R. Al-Araji, Saleh R. Al-Araji, Nawaf I. Al-Moosa, Nawaf I. Al-Moosa, } "Implementation of reconfigurable time delay digital tanlock loop", Proc. SPIE 5649, Smart Structures, Devices, and Systems II, (28 February 2005); doi: 10.1117/12.582304; https://doi.org/10.1117/12.582304

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