Paper
25 February 2005 An FPGA-based 3D image processor with median and convolution filters for real-time applications
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Proceedings Volume 5671, Real-Time Imaging IX; (2005) https://doi.org/10.1117/12.594220
Event: Electronic Imaging 2005, 2005, San Jose, California, United States
Abstract
Median Filtering and Convolution operations constitute 60-70% of the preprocessing operations performed on digital images. Software implementations of 3D filters in general-purpose processors do not match the speed requirements for real-time performance. Field Programmable Gate Arrays (FPGAs) support reconfigurable architectures that are sufficiently flexible to implement more than one operation in the existing hardware, yielding higher speed for real-time execution. We present a linear systolic array architecture for median filtering, that implements bit-serial searching and majority voting. The unique arrangement of line delay units endows parallelism to the bit-serial median finding algorithm. Convolution operation, based on the fast embedded multiplier units in the FPGA and an optimized Carry Save Adder array is also presented. The application of the above designs to 3D image preprocessing is described. A voxel rate of 220MHz is achieved for median filtering and 277MHz for convolution operation.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sharmila Venugopal, Carlos Raul Castro-Pareja, and Omkar S. Dandekar "An FPGA-based 3D image processor with median and convolution filters for real-time applications", Proc. SPIE 5671, Real-Time Imaging IX, (25 February 2005); https://doi.org/10.1117/12.594220
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Cited by 4 scholarly publications.
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KEYWORDS
Digital filtering

3D image processing

Convolution

Field programmable gate arrays

Image processing

Image filtering

Clocks

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