8 March 2005 Energy-efficient H.264 video decoding on VLIW embedded processors
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The energy consumption profiling of the H.264 video decoder on VLIW embedded processors using the Trimaran simulator is conducted. Based on this study, we observe that the branch operations in the quarter-pixel (QP) interpolation and the DCT slow down the issue rate of the VLIW processors. Then, several new instruction architecture sets are proposed to address this issue. These new instructions can be used to speedup the issue rate, and reduce the total energy consumption. Finally, experimental results of the proposed instruction-level power-efficient strategies on the TI C6416 processor are reported and discussed.
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Yu Hu, Yu Hu, Qing Li, Qing Li, C.-C. Jay Kuo, C.-C. Jay Kuo, } "Energy-efficient H.264 video decoding on VLIW embedded processors", Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.589673; https://doi.org/10.1117/12.589673


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