8 March 2005 Instruction-level power dissipation in the Intel XScale embedded microprocessor
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We present an instruction-level power dissipation model of the Intel XScale microprocessor. The XScale implements the ARM ISA, but uses an aggressive microarchitecture and a SIMD Wireless MMX co-processor to speed up execution of multimedia workloads in the embedded domain. Instruction-Level power modelling was first proposed by Tiwari et. al in 1994. Adaptations of this model have been found to be applicable to simple ARM processors. Research also shows that instructions can be clustered into groups with similar energy characteristics. We adapt these methodologies to the significantly more complex XScale processor. We characterize the processor in terms of the energy costs of opcode execution, operand values, pipeline stalls etc. through accurate measurements on hardware. This instruction-based (rather than microarchitectural) approach allows us to build a high-speed power-accurate simulator that runs at MIPS-range speeds, while achieving accuracy better than 5%. The processor core accounts only for a portion of overall power consumption, and we move beyond the core to explore the issues involved in building a SystemC simulation framework that models power dissipation of complete systems quickly, flexibly and accurately.
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Ankush Varma, Ankush Varma, Eric Debes, Eric Debes, Igor Kozintsev, Igor Kozintsev, Bruce Jacob, Bruce Jacob, } "Instruction-level power dissipation in the Intel XScale embedded microprocessor", Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.585564; https://doi.org/10.1117/12.585564

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