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22 January 2005 Manufacturability: from design to SPC limits through "corner-lot" characterization
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Abstract
Texas Instruments’ Digital Micro-mirror Device, is used in a wide variety of optical display applications ranging from fixed and portable projectors to high-definition television (HDTV) to digital cinema projection systems. A new DMD pixel architecture, called "FTP", was designed and qualified by Texas Instruments DLPTMTM Group in 2003 to meet increased performance objectives for brightness and contrast ratio. Coordination between design, test and fabrication groups was required to balance pixel performance requirements and manufacturing capability. "Corner Lot" designed experiments (DOE) were used to verify "fabrication space" available for the pixel design. The corner lot technique allows confirmation of manufacturability projections early in the design/qualification cycle. Through careful design and analysis of the corner-lot DOE, a balance of critical dimension (cd) "budgets" is possible so that specification and process control limits can be established that meet both customer and factory requirements. The application of corner-lot DOE is illustrated in a case history of the DMD "FTP" pixel. The process for balancing test parameter requirements with multiple critical dimension budgets is shown. MEMS/MOEMS device design and fabrication can use similar techniques to achieve agressive design-to-qualification goals.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Timothy J. Hogan, James C. Baker, Lisa Wesneski, Robert S. Black, and Dave Rothenbury "Manufacturability: from design to SPC limits through "corner-lot" characterization", Proc. SPIE 5716, Reliability, Packaging, Testing, and Characterization of MEMS/MOEMS IV, (22 January 2005); https://doi.org/10.1117/12.591725
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