Wafer level packaging, as well as, chip to wafer bonding has become reliable techniques for MOEMS and MEMS packaging. The main advantage of wafer level processing includes economy of scale and high throughputs. This requires high yielding wafers and a high degree of reproducibility. When these criteria cannot be met, chip to wafer packaging offers an intermediate solution to address the known-good-die concerns. A variety of packaging methods have come to fruition lately as the result of earnest research efforts. Many of these techniques focus on low temperature processing to meet the demands of nanotechnology and integrated materials and systems. Almost categorically, the miniaturization of devices has led to a need for reduced temperature processing to control thermal expansion, dimensional stability, material compatibility, and inclusion of processing circuits. Novel devices made from hot embossed plastics or heterostructures of compound semiconductors require new fabrication and packaging methods. Several wafer bonding options are available ranging from glass seals, low temperature metal based systems, plasma activated direct bonding techniques, and plastic to plastic bonding methods. Critical control of temperature profiles, applied force uniformity and surface preparation give the packaging engineer a wide range of choices for successful device packaging. Prior to 1st level packaging efforts engineered starting materials in the form of laminated substrates can greatly assist in process simplification. The following article describes methods and techniques to create starting materials and use these advanced substrates to the fullest extent for simplified device fabrication. The bonding and patterning techniques use in the front end are also the basis for packaging techniques needed to utilize new methods for wafer level packaging and chip to wafer bonding methods.