Challenges for on-chip optical interconnects

Kenneth C. Cadien; Miriam R. Reshotko; Bruce A. Block; Audrey M. Bowen; David L. Kencke; Paul Davids

doi:10.1117/12.591163

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7 March 2005 Challenges for on-chip optical interconnects

Kenneth C. Cadien, Miriam R. Reshotko, Bruce A. Block, Audrey M. Bowen, David L. Kencke, Paul Davids

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Proceedings Volume 5730, Optoelectronic Integration on Silicon II; (2005) https://doi.org/10.1117/12.591163
Event: Integrated Optoelectronic Devices 2005, 2005, San Jose, California, United States

Abstract

As integrated circuit interconnect dimensions continue to shrink and signaling frequencies increase, interconnect performance degrades. The performance degradation is due to several factors such as power consumption, cross-talk, and signal attenuation. On-chip optical interconnects are a potential solution to these scaling issues because they offer the promise of providing higher bandwidth. In this paper, progress on the major on-chip optical building blocks will be reviewed. It will be shown that significant advances have been made in the design and fabrication of waveguides, detectors, and couplers. However, major challenges in high speed electrical to optical conversion and signaling remain.

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Kenneth C. Cadien, Miriam R. Reshotko, Bruce A. Block, Audrey M. Bowen, David L. Kencke, and Paul Davids "Challenges for on-chip optical interconnects", Proc. SPIE 5730, Optoelectronic Integration on Silicon II, (7 March 2005); https://doi.org/10.1117/12.591163

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