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6 May 2005 Direct imprinting of dielectric materials for dual damascene processing
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Advanced microprocessors require several (eight or more) levels of wiring to carry signal and power from transistor to transistor and to the outside world. Each wiring level must make connection to the levels above and below it through via/contact layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace two photolithography steps. Further efficiencies are possible if the imprint resist material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael D. Stewart, Jeffery T. Wetzel, Gerard M. Schmid, Frank Palmieri, Ecron Thompson, Eui Kyoon Kim, David Wang, Ken Sotodeh, Kane Jen, Stephen C. Johnson, Jianjun Hao, Michael D. Dickey, Yukio Nishimura, Richard M. Laine, Douglas J. Resnick, and C. Grant Willson "Direct imprinting of dielectric materials for dual damascene processing", Proc. SPIE 5751, Emerging Lithographic Technologies IX, (6 May 2005);


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