In recent years as transistor gate lengths are driven to 50nm and below, several new advanced transistor architectures have been introduced. These transistor structures require the use of distinctly different materials and process technology, each of which imposes new challenges. In the early development phase of our FinFET technology, which utilizes Silicon On Insulator (SOI), very large overlay errors were observed. These overlay errors could be as much as ten times larger than the overlay capability of the state of the art exposure tools used.
Traditionally when analyzing such overlay errors we characterize the systematic or correctable components and the residual errors. The modeling of these overlay errors in terms of grid and intrafield components is well understood and provides an extremely effective means of detecting registration errors associated with the exposure tools. Nevertheless, when large overlay errors are observed, the tendency remains to suspect that the exposure tool is the cause of the overlay errors. In these situations alignment often and very quickly becomes the focus of attention.
By using experimental splits and appropriate analysis techniques, we were able to identify the specific process steps and equipment responsible. This allowed those process steps to be replaced by alternative integration strategies, before the technology was finalized. By detection of these errors early in the development phase and by working closely with integration, a well characterized process, eliminating FinFET material and process induced overlay errors can be achieved. In this paper we report on the methodology used and show that overlay performance can be achieved consistent with the capabilities of the state of the art exposure tools used.