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12 May 2005 Etch modeling for accurate full-chip process proximity correction
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The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman et al. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.
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Daniel F. Beale and James P. Shiely "Etch modeling for accurate full-chip process proximity correction", Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2005);

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