12 May 2004 Lithography enabling for the 65 nm node gate layer patterning with alternating PSM
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Abstract
This paper presents the application of double exposure alternating phase shift mask (APSM) lithography to the 65nm node gate layer. An integrated approach involving optimization of the layout design rules, APSM synthesis, Optical Proximity Correction (OPC), mask manufacturing process, and wafer patterning process has been employed to scale gate layer critical dimensions from the 90nm node to the 65 nm node with no loss in focus or exposure process window. The paper focuses on some of challenges for achieving a production-worthy APSM solution, including discussions of APSM flow development along with aspects of OPC model calibration, OPC performance, CD control, and OPC validation. Patterning results from the application of APSM to the gate level of a state-of-the-art 65nm node random logic technology are presented.
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Alexander Tritchkov, Alexander Tritchkov, Seongtae Jeong, Seongtae Jeong, Christopher Kenyon, Christopher Kenyon, } "Lithography enabling for the 65 nm node gate layer patterning with alternating PSM", Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2004); doi: 10.1117/12.601606; https://doi.org/10.1117/12.601606
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