12 May 2004 Optimized hardware and software for fast full-chip simulation
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Lithography simulation is an increasingly important part of semiconductor manufacturing due to the decreasing k1 value. It is not only required in lithography process development, but also in RET design, RET verification, and process latitude analysis, from library cells to full-chip. As the design complexity grows exponentially, pure software based simulation tools running on general-purpose computer clusters are facing increasing challenges in meeting today’s requirements for cycle time, coverage, and modeling accuracy. We have developed a new lithography simulation platform (TachyonTM) which achieves orders of magnitude speedup as compared to traditional pure software simulation tools. The platform combines innovations in all levels of the system: algorithm, software architecture, cluster-level architecture, and proprietary acceleration hardware using application specific integrated circuits. The algorithm approach is based on image processing, fundamentally different from conventional edge-based analysis. The system achieves superior model accuracy than conventional full-chip simulation methods, owing to its ability to handle hundreds of TCC kernels, using either vector or scalar optical model, without impacting throughput. Thus first-principle aerial image simulation at the full-chip level can be carried out within minutes. We will describe the hardware, algorithms and models used in the system and demonstrate its applications of the full chip verification purposes.
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Yu Cao, Yen-Wen Lu, Luoqi Chen, Jun Ye, "Optimized hardware and software for fast full-chip simulation", Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2004); doi: 10.1117/12.600951; https://doi.org/10.1117/12.600951

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