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5 May 2005 Design and process limited yield at the 65-nm node and beyond
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Immersion lithography at 193nm has emerged as the leading contender for critical patterning through the 32nm technology node. Super-high NA, along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control at intra-wafer and intra-field levels. Furthermore, interactions of critical dimensions, profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint DFM and APC strategies at the 65nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kevin Monahan and Brian Trafas "Design and process limited yield at the 65-nm node and beyond", Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005);

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