Translator Disclaimer
5 May 2005 Evaluating design for manufacturing with process capability analysis
Author Affiliations +
The shrinking of the dimensions for each new process generation increases the challenges for lithography significantly. In order to guarantee manufacturability for future process generations, a strong interaction between lithography and design is required. A quantitative measure for the manufacturability is of key importance for driving the improvements in the design for manufacturing process. Aerial image slopes or contrasts in simulated images provide a measure for the sensitivity to process variations, but do not take the statistical process variation into account. This may result in sub-optimal choices in the design for manufacturing process. This paper discusses the process capability analysis and provides an optimal design with corresponding imaging conditions, taking the statistical fluctuations of exposure dose and focus into account. The mean CD value and the CD spread are calculated as a function of the amount of variation in the process variables like focus and exposure dose. Comparing these distribution parameters to the process specifications yields the so-called process capability index as a quantitative measure for the manufacturability. Another advantage is the possibility to include the effect of mask errors on the manufacturability. Until now, however, this method had only been demonstrated for line space features. In this paper we extend the process capability analysis method for calculating the manufacturability of arbitrary layouts. The analysis is demonstrated in an evaluation of the manufacturability of various gate layer designs, both conventional as well as litho-driven re-designs.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Johannes van Wingerden, Laurent Le Cam, Manish Garg, Yuri Aksenov, and Peter Dirksen "Evaluating design for manufacturing with process capability analysis", Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005);

Back to Top