5 May 2005 Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration
Author Affiliations +
Abstract
Design tools exploit design hierarchy for speed, efficiency and reuse. Conventional OPC solutions, however, do not fully exploit such structures and hence are not very efficient. Since a cell may be instantiated thousands of times in a design, this implies that redundant OPC operations are usually applied, at the cell instance level, repeatedly to the same master cell within the context of the design. Some cell-based OPC studies have been performed in an attempt to alleviate such inefficiency. For example, Gupta, Heng and Lavin have shown that a simple cell-based (book-based) OPC approach has negligible OPC imperfectness around cell boundaries but has an average P/D speed-up, where P is the number of master placement cells and D is the number of master cells. This article presents an alternative approach to the above mentioned works. Here, we illustrate that it is not only possible to apply OPC on a per-cell basis, but also to "stitch" already corrected cells along their interacting areas together to form a proximity corrected final layout. Because of the stitching steps, our approach can handle more practical and complicated hierarchical layouts than those described in Gupta et al. and achieve OPC quality equivalent to that obtained using conventional OPC methods. In addition, since our approach performs the majority of OPC work at the cell level, we can maintain the runtime savings comparable to that demonstrated by Gupta et al. This technique of localized OPC reconfiguration can be extended to handle applications such as manufacturing ECO handling and design re-spins.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Xin Wang, Mark Pillof, Hongbo Tang, Clive Wu, "Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration", Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.599830; https://doi.org/10.1117/12.599830
PROCEEDINGS
7 PAGES


SHARE
Back to Top