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5 May 2005 Investigation of model-based physical design restrictions (Invited Paper)
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As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kevin Lucas, Stanislas Baron, Jerome Belledent, Robert Boone, Amandine Borjon, Christophe Couderc, Kyle Patterson, Lionel Riviere-Cazaux, Yves Rody, Frank Sundermann, Olivier Toublan, Yorick Trouiller, Jean-Christophe Urbani, and Karl Wimmer "Investigation of model-based physical design restrictions (Invited Paper)", Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005);

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