5 May 2005 Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era
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Abstract
As lithographers continue to implement more exotic and complex Resolution Enhancement Techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are be-coming increasingly valuable to help identify random and systematic defects that occur due to mask tolerance ex-cursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or Process Window Qualification, is a KLA-Tencor product* using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM’s 300mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models; 2) identification of non-obvious lithographic features that limit common process windows; 3) providing input for long-term design for manufacturability (DfM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65nm and a 90nm CMOS process.
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Mary Jane Brodsky, Mary Jane Brodsky, Scott Halle, Scott Halle, Vickie Jophlin-Gut, Vickie Jophlin-Gut, Lars Liebmann, Lars Liebmann, Don Samuels, Don Samuels, Gary Crispo, Gary Crispo, Kourosh Nafisi, Kourosh Nafisi, Vijay Ramani, Vijay Ramani, Ingrid Peterson, Ingrid Peterson, } "Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era", Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.599865; https://doi.org/10.1117/12.599865
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