2 June 2005 A comparison of lattice decoding algorithms in hardware implementation
Author Affiliations +
Multiple-input multiple-output wireless systems use multiple antennas in both transmitter and receiver. The huge capacity of this multi-environment system has attracted intensive interests in recent years. Hardware implementation of MIMO lattice decoder becomes a challenging task because of the complexity of the lattice decoding algorithms. This paper compares two typical lattice decoding algorithms in hardware implementations. The data dependency among the iterative closest lattice point search procedure is examined and the possibilities of parallel implementation are explored. Parallel architectures are designed for each algorithm and are prototyped on two different hardware platforms: FPGA and DSP. Decoding rate and bit error rate are compared between the two algorithms. The performance of different hardware platforms is investigated as well. The experimental results show that the FPGA-based AV algorithm decoder supports 17.6Mbit/s decoding rate when mapped on a Xilinx Virtex2 1000 FPGA, and is more than 7 times faster than the VB algorithm decoder on the same hardware. To achieve the compatible bit error rate performance, FPGA based lattice decoder provides an order of magnitude faster decoding rate than the DSP decoder using the same algorithm.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jing Ma, Jing Ma, Cao Liang, Cao Liang, Xinming Huang, Xinming Huang, "A comparison of lattice decoding algorithms in hardware implementation", Proc. SPIE 5819, Digital Wireless Communications VII and Space Communication Technologies, (2 June 2005); doi: 10.1117/12.604205; https://doi.org/10.1117/12.604205

Back to Top