Paper
2 June 2005 A high data rate universal lattice decoder on FPGA
Jing Ma, Xinming Huang, Swapna Kura
Author Affiliations +
Abstract
This paper presents the architecture design of a high data rate universal lattice decoder for MIMO channels on FPGA platform. A phost strategy based lattice decoding algorithm is modified in this paper to reduce the complexity of the closest lattice point search. The data dependency of the improved algorithm is examined and a parallel and pipeline architecture is developed with the iterative decoding function on FPGA and the division intensive channel matrix preprocessing on DSP. Simulation results demonstrate that the improved lattice decoding algorithm provides better bit error rate and less iteration number compared with the original algorithm. The system prototype of the decoder shows that it supports data rate up to 7Mbit/s on a Virtex2-1000 FPGA, which is about 8 times faster than the original algorithm on FPGA platform and two-orders of magnitude better than its implementation on a DSP platform.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jing Ma, Xinming Huang, and Swapna Kura "A high data rate universal lattice decoder on FPGA", Proc. SPIE 5819, Digital Wireless Communications VII and Space Communication Technologies, (2 June 2005); https://doi.org/10.1117/12.604182
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Cited by 1 scholarly publication.
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KEYWORDS
Digital signal processing

Field programmable gate arrays

Clocks

Optical spheres

Algorithm development

Prototyping

Antennas

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