Mismatch analysis and simulation is crucial for modern analog design with submicron technologies, where transistors tend to be biased in weak and moderate inversion regions because of the down shrinking of power supply voltage. For optimum analog design where speed, power consumption, area, noise, and accuracy need to be carefully traded off, it is crucial to have available a precise estimation of transistor mismatch in order to avoid overdesign and consequently sacrify unnecessarily speed, power consumption, and area. In this paper we will provide experimental mismatch measurements of different 0.35um CMOS technologies. Each technology has been characterized for a large number of transistor sizes (25-30), by sweeping different width and length values. A large number of transistor curves are measured ranging over different possible biasing conditions. A recent mismatch model will be used to fit the data, and extract electrical parameters. Some of those parameters will be used to adjust the measured mismatch. As a result, a set of standard deviations and correlation coefficients result for the statistical characterization of the mismatch responsible parameters. The resulting electrical parameters, and statistical mismatch
parameters are then used in the Spectre simulator of Cadence design environment, to implement the mismatch models using the AHDL behavioral level Spectre description language. The paper shows good agreement between measured data, predicted data, and simulated data.