30 June 2005 Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
Author Affiliations +
Abstract
One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry, meaning that memory elements are the main source of noise in digital circuits. This paper faces the application of clock-gating, a well known low-power technique, to the reduction of switching-noise generation. Sources of switching noise in master-slave flip-flops will be analyzed. It will be shown how different solutions for the clock-gated logic show very different results regarding switching-noise generation. Illustrative examples characterized through HSPICE simulations, as well as the application of clock-gating to 16-bit synchronous counter as demonstrator, will provide useful design guidelines for reduction of switching noise generation.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Pilar Parra, Pilar Parra, Javier Castro, Javier Castro, Manuel Valencia, Manuel Valencia, Antonio J. Acosta, Antonio J. Acosta, } "Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608276; https://doi.org/10.1117/12.608276
PROCEEDINGS
12 PAGES


SHARE
Back to Top