Translator Disclaimer
30 June 2005 Built-in test engine and fault simulation for memory
Author Affiliations +
In this paper an on-chip method for testing high performance memory devices will be presented. This new technique occupies minimal area and retains the full flexibility of existing methods for the dynamic introduction of new test patterns. This is achieved through microcode test instructions and the associated on-chip state machine. The proposed methodology will enable at-speed testing of memory devices, reducing the overall test time. The relevancy of this work is placed in context with an introduction to memory testing and the techniques and algorithms generally used today. Additionally, we examine the use of fault simulation in methodology evaluation for memory test. Finally we present a prototype design for the implementation of this methodology that incurs minimal test latency and provides a programmable interface to enable varying fault coverage and location patterns.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
P. McEvoy and R. Farrell "Built-in test engine and fault simulation for memory", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005);


Back to Top