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30 June 2005 CHIADO: compilation of high-level computationally intensive algorithms to dynamically reconfigurable computing systems
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Abstract
Reconfigurable computing has already confirmed a significant potential for accelerating certain computing tasks. However, the most successful applications relied on user expertise to design a specific architecture implemented by the hardware structures of the reconfigurable computing device. Hence, one of the most challenging issues is to map, efficiently and automatically, computations (described in software programming languages) to reconfigurable computing devices. This paper presents CHIADO, a research project aiming a compiler framework to map efficiently software programs to reconfigurable computing platforms, especially the ones based on FPGA (Field-Programmable Gate Array) devices. The framework is also intended to support research of new optimization techniques. The project, based on our previous work on compiling Java bytecodes to FPGAs, focuses on high-performance solutions, schemes to estimate the impact of some transformations supported by the compiler (partial/full loop unrolling), and schemes to take advantage of dynamic reconfiguration (e.g., temporal partitioning). This paper gives an overview about the CHIADO project, shows the framework, and enumerates the main project goals.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Joao M. P. Cardoso "CHIADO: compilation of high-level computationally intensive algorithms to dynamically reconfigurable computing systems", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608805
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