Translator Disclaimer
Paper
30 June 2005 Data-driven array architectures: a rebirth?
Author Affiliations +
Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608799
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain
Abstract
The von Neumann-style architectures have been tremendously well succeeded by taking advantage of the Moore’s law. It is now understood that, it will be very difficult to meet the supercomputing demands of the future computing systems with this style of microprocessor architectures. Most nowadays applications require high-performance for processing data streams. Being dataflow computing a natural paradigm to process data streams, architectures based on dataflow principles are emerging as a way to meet the supercomputing demands. Data-driven arrays, introduced in the 80’s, are examples of such architectures. They devised a scalable and effective fashion to directly support the dataflow model of computation and have been revived by a number of reconfigurable architectures (e.g., KressArray, WaveScalar, and XPP). Those coarse-grained reconfigurable architectures with dataflow semantics depict interesting achievements with respect to performance and programming methodologies, when compared to other computing platforms. This paper presents the most interesting data-driven array architectures. Trends and open issues related to a number of properties at architectural level and to compilation techniques are enumerated and discussed. A number of features are illustrated, especially the support for hardware virtualization, speculative configuration, and software pipelining. Examples using the PACT XPP reconfigurable array are shown. Those examples include the ADPCM decoder, from the MediaBench repository, and LeeDCT, an optimized DCT algorithm.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Joao M. P. Cardoso "Data-driven array architectures: a rebirth?", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608799
PROCEEDINGS
12 PAGES


SHARE
Advertisement
Advertisement
Back to Top