30 June 2005 Hardware implementation of the wavelet transform for JPEG2000
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Abstract
In this paper we shall propose and examine an VLSI architecture for the integer-to-integer wavelet transform which is used by JPEG2000 standard for lossless compression. In order to achieve a fully utilization of hardware resources independently of the bit-depth of the input data, on-line arithmetic (digit-serial computation) is proposed to carry out this architecture. Besides, a high throughput is achieved thanks to the high degree of parallelism that on-line arithmetic allows. The design has been simulated and implemented using Xilinx FPGA device, and its main results are provided.
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J. Hormigo, J. M. Prades, J. Villalba, E. Zapata, "Hardware implementation of the wavelet transform for JPEG2000", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608221; https://doi.org/10.1117/12.608221
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