Net order optimization in analog net bundles

Thomas Jambor; Lars Schreiner; Markus Olbrich; Erich Barke

doi:10.1117/12.608624

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30 June 2005 Net order optimization in analog net bundles

Thomas Jambor, Lars Schreiner, Markus Olbrich, Erich Barke

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608624
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

This paper presents a new approach to optimize net order in analog busses. It is used for the PARasitic SYmmetric router (PARSY), which routes net bundles, e.g. busses or differential pairs, maintaining parasitic symmetry and limiting differential coupling. The router is mainly devoted to analog signal interconnect but can also be used for critical digital busses. Net bundles have a fixed order, because wire crossing is not allowed in net bundle segments to enforce symmetry. Wires inside net bundle segments are generated by module generators. Connecting cell terminals to the first or the last net bundle segment is complex, because the cell terminals can vary in geometry and placement. Therefore, an assignment between nets and wires (net order) in a segment is required. This assignment does not affect the order in which nets or net bundles are routed sequentially. The optimization objective for the connections from net bundle segments to terminals is to minimize the number of crossings and the length difference, while maintaining symmetry if possible. Therefore, a net order has to be calculated, which globally optimizes these criteria for all terminal connections. Different net orders can be computed from the placement of terminals, which have to be connected to a net bundle segment. An additional order is calculated from these net orders, which contains the most characteristic features of all net orders. For all net orders costs are evaluated, and the one with the lowest cost is chosen.

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Thomas Jambor, Lars Schreiner, Markus Olbrich, and Erich Barke "Net order optimization in analog net bundles", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608624

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