23 May 2005 A physical understanding of the noise performance of MOS transistors for wireless and lightwave applications in the giga-bit regime (Invited Paper)
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Proceedings Volume 5844, Noise in Devices and Circuits III; (2005) https://doi.org/10.1117/12.609965
Event: SPIE Third International Symposium on Fluctuations and Noise, 2005, Austin, Texas, United States
Abstract
Functional requirements for modern narrow-band and wide-band wireless and lightwave communication systems place stringent demands on speed and noise behavior of circuits and devices used to design them. MOS technology in the nanometer regime continues to be the low-cost high-performance workhorse driving innovations for these applications. In this paper, we trace the developments in the modeling of noise in MOS transistors as the device channel lengths shrink by a factor or a thousand from tens of micrometers to tens of nanometers. The impact of scaling on classical noise mechanisms is explained. Also, generation of new noise sources as a result of scaling are also described. This leads to a better physical understanding of the noise behavior of these devices. Methods of eliminating some of these noise sources by suitable choice of materials and modifications in device structure are explained. Application of this understanding to the practical design and layout of low-noise high-performance circuits is illustrated. As a result, the noise performance of MOS devices has improved by almost an order of magnitude making them an ideal choice for low-noise communication electronics design. Research continues as the channel lengths shrink further.
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R. P. Jindal, R. P. Jindal, } "A physical understanding of the noise performance of MOS transistors for wireless and lightwave applications in the giga-bit regime (Invited Paper)", Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); doi: 10.1117/12.609965; https://doi.org/10.1117/12.609965
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