A simple noise modeling based testing of CMOS analog integrated circuits

Siva Yellampalli; Ashok Srivastava

doi:10.1117/12.609253

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23 May 2005 A simple noise modeling based testing of CMOS analog integrated circuits

Siva Yellampalli, Ashok Srivastava

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Proceedings Volume 5844, Noise in Devices and Circuits III; (2005) https://doi.org/10.1117/12.609253
Event: SPIE Third International Symposium on Fluctuations and Noise, 2005, Austin, Texas, United States

Abstract

A technique for testing CMOS analog integrated circuits is presented which is based on an analysis of the noise behavior of the circuit under test (CUT). The technique is simple and new. The CUT in the present work is an integrated CMOS amplifier circuit designed in a standard 1.5 μm n-well CMOS process for operation at ±;2.5 V. The bridging faults simulating possible manufacturing defects have been introduced using fault injection transistors. The faults in the CUT are detected by observing the variation in the noise at the output of CUT, which is the sum of noise contributed from each component in the circuit. An analytical noise model of the CUT has been developed with and without faults and results are compared with the corresponding data obtained from the simulation studies using SPICE.

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Siva Yellampalli and Ashok Srivastava "A simple noise modeling based testing of CMOS analog integrated circuits", Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); https://doi.org/10.1117/12.609253

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