23 May 2005 High frequency noise of SOI MOSFETs: performances and limitations (Invited Paper)
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Proceedings Volume 5844, Noise in Devices and Circuits III; (2005) https://doi.org/10.1117/12.609669
Event: SPIE Third International Symposium on Fluctuations and Noise, 2005, Austin, Texas, United States
In this paper, the performances and limitations related to the high frequency noise properties of SOI MOSFET Technology are investigated. The study is conducted through powerful analytical noise parameters calculation, experimental data, and physical based drift-diffusion noise modeling. In addition to the noise generated by the inner part of the active device, the influence of access resistances, overlap/fringing capacitances, tunneling gate current are discussed qualitatively and quantitatively. The paper ends up with a critical discussion related to the "New Era SOI Technology" to come and its influence on the noise performance.
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Francois Danneville, Francois Danneville, Guillaume Pailloncy, Guillaume Pailloncy, Alexandre Siligaris, Alexandre Siligaris, Benjamin Iniguez, Benjamin Iniguez, Gilles Dambrine, Gilles Dambrine, } "High frequency noise of SOI MOSFETs: performances and limitations (Invited Paper)", Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); doi: 10.1117/12.609669; https://doi.org/10.1117/12.609669

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