Lithography simulation is an integral part of semiconductor manufacturing. It is not only required in lithography process development, but also in RET design, RET verification, and process latitude analysis, from library cells to full-chip tape out. Two RET design checking flows are examined and compared. In the first flow, an image contour is simulated from post-OPC, GDSII data at best focus and exposure conditions. RET design defects are identified by comparing the calculated contours with the pre-OPC design data. To check lithography manufacturability across the typical IC process window, the second RET verification flow simulates image contours at multiple focus and exposure conditions. These RET design checking flows are implemented on new platform that combines a hardware accelerated computational engine with a new analysis method to numerically evaluate the lithographic printing and mask manufacturing challenges for a given design layout. The algorithm approach in this new system is based on image processing which is fundamentally different from conventional edge-based analysis. Specific examples of a mask aware RET verification flow leveraging this new platform and method will be provided with speed and accuracy benchmarks. Through the high speed computation of lithographic images from full chip data, many opportunities for novel and cost effective post layout lithography verification options become available. By combining the new platform with analysis steps relevant in leading edge photomask manufacturing, it may become possible to reduce the risks inherent in advanced technology tape outs while improving layout to mask fabrication cycle time and cost.