Model based full-chip lithography verification has been proven as a mask sign off solution to prevent patterning failures caused by design/OPC (Optical Proximity Correction) before mask data tape out. Furthermore, as the fast turn around time is achieved through scalable distributed processing for very large data after mask synthesis conversion such as assist feature and OPC, model-based full-chip verification can take advantages of RET (Resolution Enhancement Technique)/OPC recipe development. In previous studies, we introduced the full-chip verification methodologies for mask sign off flow in production and for RET/OPC optimization flow in process development stage for sub-wavelength lithography processes in general.
In this paper, we demonstrated the layer-specific verifications for critical layers for 65nm lithography process development. For poly layer, we performed various types of checks such as fatal pinch/bridge hotspots, CD variations, line-end/space-end errors, assist feature printability, MMEF (Mask Error Enhancement Factor) and geometrical (Mask Rule/structural) checks considering the mask manufacturing constraints. We compared hyper NA (Numerical Aperture)illumination using immersion lithography with the double expose alternating PSM (Phase Shift Mask) lithography. For metal layer, various full-process window coverage verification methodologies were discussed.