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16 September 2005 A design of online scheme for evaluation of multinomials
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We present an online arithmetic scheme for hardware evaluation of multinomials arising in Bayesian networks. The design approach consists of representing the multinomial in a factored form as an arithmetic circuit which is then partitioned into subgraphs and mapped to FPGA hardware as a network of online modules connected serially and operating in overlapped manner. This minimizes the interconnect demand without a drastic increase in computation latency. We developed a partitioning/mapping algorithm, designed basic radix-2 online operators and modules, and determined their cost/performance characteristics. We also evaluated the cost/performance characteristics of implementing a Bayesian network on an FPGA chip.
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Pouya Dormiani, David Omoto, Pavan Adharapurapu, and Milos D. Ercegovac "A design of online scheme for evaluation of multinomials", Proc. SPIE 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV, 59100S (16 September 2005);

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