11 October 2005 FPGA based, DSP board for LLRF 8-Channel SIMCON 3.0 Part I: Hardware
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The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the VUV-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layers, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACC1 module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0 encouraged us to enter the design of SIMCON 3.1 possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0 is a modular solution, while SIMCON 3.1 will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one, after branching off in this version of the SIMCON, will be continued.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Wojciech Giergusiewicz, Waldemar Koprek, Wojciech Jalmuzna, Krzysztof T. Pozniak, Ryszard S. Romaniuk, "FPGA based, DSP board for LLRF 8-Channel SIMCON 3.0 Part I: Hardware", Proc. SPIE 5948, Photonics Applications in Industry and Research IV, 59480D (11 October 2005); doi: 10.1117/12.622478; https://doi.org/10.1117/12.622478

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