29 September 2005 Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors
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Proceedings Volume 5957, Infrared Photoelectronics; 595701 (2005); doi: 10.1117/12.626828
Event: Congress on Optics and Optoelectronics, 2005, Warsaw, Poland
Infrared sensor designers have long maximized S/N ratio by employing pixel-based amplification in conjunction with supplemental noise suppression. Instead, we suppress photodiode noise using novel SoC implementation with simple three transistor pixel; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The tapered reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Integrated in a 2.1M pixel imager developed for generating high definition television, random noise is ~8e- at video rates to 225MHz. Random noise of ~30e- would otherwise be predicted for the 5μm by 5μm pixels having 5.5fF detector capacitance with negligible image lag. Minimum sensor S/N ratio is 52dB with 1920 by 1080 progressive readout at 60Hz, 72Hz and 90Hz. Fixed pattern noise is <2 DN via on-chip signal processing.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lester J. Kozlowski, "Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors", Proc. SPIE 5957, Infrared Photoelectronics, 595701 (29 September 2005); doi: 10.1117/12.626828; https://doi.org/10.1117/12.626828


CCD image sensors

Charge-coupled devices

CMOS sensors

System on a chip


CCD cameras

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