24 June 2005 A novel parallel architecture for local histogram equalization
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Proceedings Volume 5960, Visual Communications and Image Processing 2005; 59605Z (2005) https://doi.org/10.1117/12.633383
Event: Visual Communications and Image Processing 2005, 2005, Beijing, China
Abstract
Local histogram equalization is an image enhancement algorithm that has found wide application in the pre-processing stage of areas such as computer vision, pattern recognition and medical imaging. The computationally intensive nature of the procedure, however, is a main limitation when real time interactive applications are in question. This work explores the possibility of performing parallel local histogram equalization, using an array of special purpose elementary processors, through an HDL implementation that targets FPGA or ASIC platforms. A novel parallelization scheme is presented and the corresponding architecture is derived. The algorithm is reduced to pixel-level operations. Processing elements are assigned image blocks, to maintain a reasonable performance-cost ratio. To further simplify both processor and memory organizations, a bit-serial access scheme is used. A brief performance assessment is provided to illustrate and quantify the merit of the approach.
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Mesrob I. Ohannessian, Mesrob I. Ohannessian, Ghinwa F. Choueiter, Ghinwa F. Choueiter, Hassan Diab, Hassan Diab, } "A novel parallel architecture for local histogram equalization", Proc. SPIE 5960, Visual Communications and Image Processing 2005, 59605Z (24 June 2005); doi: 10.1117/12.633383; https://doi.org/10.1117/12.633383
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