14 October 2005 Focal-plane CMOS wavelet feature extraction for real-time pattern recognition
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Kernel-based pattern recognition paradigms such as support vector machines (SVM) require computationally intensive feature extraction methods for high-performance real-time object detection in video. The CMOS sensory parallel processor architecture presented here computes delta-sigma (ΔΣ)-modulated Haar wavelet transform on the focal plane in real time. The active pixel array is integrated with a bank of column-parallel first-order incremental oversampling analog-to-digital converters (ADCs). Each ADC performs distributed spatial focal-plane sampling and concurrent weighted average quantization. The architecture is benchmarked in SVM face detection on the MIT CBCL data set. At 90% detection rate, first-level Haar wavelet feature extraction yields a 7.9% reduction in the number of false positives when compared to classification with no feature extraction. The architecture yields 1.4 GMACS simulated computational throughput at SVGA imager resolution at 8-bit output depth.
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Ashkan Olyaei, Ashkan Olyaei, Roman Genov, Roman Genov, } "Focal-plane CMOS wavelet feature extraction for real-time pattern recognition", Proc. SPIE 5969, Photonic Applications in Biosensing and Imaging, 596927 (14 October 2005); doi: 10.1117/12.629237; https://doi.org/10.1117/12.629237

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