CMOS compatible vertical directional coupler for 3D optical circuits

J. K. Doylend; A. P. Knights; C. Brooks; P. E. Jessop

doi:10.1117/12.627884

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12 October 2005 CMOS compatible vertical directional coupler for 3D optical circuits

J. K. Doylend, A. P. Knights, C. Brooks, P. E. Jessop

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Proceedings Volume 5970, Photonic Applications in Devices and Communication Systems; 59700G (2005) https://doi.org/10.1117/12.627884
Event: Photonics North, 2005, Toronto, Canada

Abstract

We report simulation results for a directional coupler between silicon waveguides in different layers of a three-dimensional (3D) optical circuit. The coupling length is 1.4 mm. The device is manufacturable using standard CMOS technology provided individual waveguide layers can be vertically stacked. In simulations of coupling efficiency the design exhibits negligible loss with respect to translational and rotational misalignments of up to 0.5 μm. Efficiency degradation is less than 5% for etch depth and waveguide width variations of 0.4 μm, and less than 1 dB over the range of standard lithographic tolerances for variations from layer to layer in feature width, depth, and alignment.

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J. K. Doylend, A. P. Knights, C. Brooks, and P. E. Jessop "CMOS compatible vertical directional coupler for 3D optical circuits", Proc. SPIE 5970, Photonic Applications in Devices and Communication Systems, 59700G (12 October 2005); https://doi.org/10.1117/12.627884

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