We propose a combined cell stencil (CCS), a shot reduction method, for character projection lithography (CPL). Electron Beam Direct Writing (EBDW) has been focused on the maskless chip fabrications, in terms both of quick turn-around-time and chip fabrication cost reduction for the nano-meter VLSI processes. EDBW, however, suffers from less throughput performance than the conventional optical
lithography. CPL, which employs stencil masks to utilize the pattern beam, has been reported to reduce numbers of shots to 1/10 to 1/15 compared with the conventional variable shaped beam projection. The conventional cell stencil consists of a single cell layout pattern. The proposed CCS consists of two or more cell layouts, which are frequently connected to each other in netlists. We find frequently connected cell pairs in netlists to form new stencil patterns, as CCSes. Assuming that the frequently connected cells are usually placed close to each other on layout, timing closure will not be seriously degraded with this method. We evaluated the proposed method in terms of numbers of shots in layout patterns generated from place and route tools, whose netlists are replaced with the CCSes from the
original cells, which is completely compatible with the conventional cell-based design flow. We applied the proposed method to a microprocessor design and demonstrated 22.4% shots reduction with 4.4% area increase compared with the previously reported shot reduction method for CPL. We also carried out IWLS (International
Workshop on Logic Synthesis) benchmarks to show the reusability of the generated CCS stencil masks.