Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD
measurements. However, these measurements are not comprehensive enough, limited to a very few layout features. It is desirable to confirm lithographic process window robustly, for all the cell design features of interest, to ensure full functionality of the cell. In this work, we propose for the first time to focus on the electrical deliverables after ILT pattern quality has been initially verified by SEM visual inspection. We designed an electrically measurable SRAM
structure for a 65 nm process, to extract device and interconnect parameters depending on the lithographic process conditions, as a means to compare pattern quality of the conventional mask creation technique, Optical Proximity Correction (OPC) with ILT. We present the drawn layout, the masks created by the two technologies, and the
corresponding image simulation and silicon pattern.