9 November 2005 Implementation of random contact hole design with CPL mask by using IML technology
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Proceedings Volume 5992, 25th Annual BACUS Symposium on Photomask Technology; 599237 (2005); doi: 10.1117/12.633286
Event: SPIE Photomask Technology, 2005, Monterey, California, United States
Abstract
The contact hole imaging is a very challenge task for the optical lithography process during IC manufacturing. Lots of RETs were proposed to improve the contrast of small opening hole. Scattering Bar (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k1 contact imaging. In this study, an effective model-based SB OPC based on IML technology is implemented for contact layer at 90nm, 65nm, and 45nm nodes. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. Then, we selected the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, the model-based SB OPC is performed. Next, model OPC can be applied with the presence of SB for the entire chip. It is important to note that, for patterning at k1 near 0.35 or below, it may be necessary to include 3D mask effects with a high NA OPC model. With enhanced DOF by IML and immersion process, the low k1 production worthy contact process is feasible.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Hsu, Doug Van Den Broeke, Stephen Hsu, J. Fung Chen, Xuelong Shi, Noel Corcoran, Linda Yu, "Implementation of random contact hole design with CPL mask by using IML technology", Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 599237 (9 November 2005); doi: 10.1117/12.633286; http://dx.doi.org/10.1117/12.633286
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KEYWORDS
Photomasks

Optical proximity correction

Semiconducting wafers

Model-based design

3D modeling

Printing

Resolution enhancement technologies

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