8 November 2005 Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations
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Abstract
Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k1, e.g. k1<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k1<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.
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Ting Chen, Ting Chen, Doug Van Den Broeke, Doug Van Den Broeke, Stephen Hsu, Stephen Hsu, Michael Hsu, Michael Hsu, Sangbong Park, Sangbong Park, Gabriel Berger, Gabriel Berger, Tamer Coskun, Tamer Coskun, Joep de Vocht, Joep de Vocht, Fung Chen, Fung Chen, Robert Socha, Robert Socha, JungChul Park, JungChul Park, Keith Gronlund, Keith Gronlund, } "Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations", Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 599239 (8 November 2005); doi: 10.1117/12.633465; https://doi.org/10.1117/12.633465
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