The simulation and verification of large layout areas is becoming feasible due to the recent convergence of three factors: The ability of compact models to describe process variations, new advances in design layout representations, provided by efficient formats such as OASIS, and continuous improvement of distributed computing systems.
Traditional DRC is limited to describe the problem geometrically. Feature width and spacing used to be the main contributors to failure; however, geometric DRC's are becoming insufficient to assure pattern transfer integrity. For most sub-wavelength processes, neighboring structure effects start to become important and in some cases dominant. This work shows that a model-based verification is better equipped to deal with all the rule exemptions imposed by multiple layout configurations, since neighboring structure configurations are accounted during simulation.
Following an existing DRC paradigm, the number of layout verification objects has multiplicative domain size with respect to each of the process variables and their corresponding sampling grid. In other words, assuming three process variables (i.e. exposure, focus and mask bias) the verification domain is of size NxMxL (where N, M and L are the number of simulation points for each process variable). By creating intermediate verification data structures such as pv-Bands the number of measured process objects is reduced to two, representing maximum and minimum displacements. In addition, this work suggests that the total number of simulations needed to bind the design verification space is determined by specific process corners, specifically when those process variations refer to defocus, exposure and mask bias.