8 November 2005 Predicting wafer-level IP error due to particle-induced EUVL reticle distortion during exposure chucking
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Abstract
The mechanical distortion of an EUVL mask from mounting in an exposure tool can be a significant source of wafer-level image placement error. In particular, the presence of debris lodged between the reticle and chuck can cause the mask to experience out-of-plane distortion and in-plane distortion. A thorough understanding of the response of the reticle/particle/chuck system during electrostatic chucking is necessary to predict the resulting effects of such particle contamination on image placement accuracy. In this research, finite element modeling is employed to simulate this response for typical clamping conditions.
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Vasu Ramaswamy, Vasu Ramaswamy, Andrew Mikkelson, Andrew Mikkelson, Roxann Engelstad, Roxann Engelstad, Edward Lovell, Edward Lovell, } "Predicting wafer-level IP error due to particle-induced EUVL reticle distortion during exposure chucking", Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 59923T (8 November 2005); doi: 10.1117/12.631362; https://doi.org/10.1117/12.631362
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